With the high level of integration in semiconductor devices, the channel length of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) has become increasingly shorter. Those effects that are negligible in a long-channel model of MOSFET have become more significant, and in some cases, a major factor affecting the performance of the device. This phenomenon is called a short-channel effect. The short-channel effect may degrade electrical performance of the device, causing problems such as decreased threshold voltage of the gate, increased power consumption and reduced signal-to-noise ratio.
In order to control the short-channel effect, improvements have been made to conventional transistor devices in some aspects. For example, in one aspect, the channel of the device can be doped with more impurities such as phosphorus and boron, but this may cause carrier mobility decrease in the channel; in another aspect, stress in the channel can be enhanced, but strain increase is limited by the conventional SiGe Positive-channel Metal Oxide Semiconductor (PMOS) strained silicon technique; and in yet another aspect, the thickness of the gate oxide can be reduced, but we still face technological constraints: the reduction in thickness of the gate oxide does not match the reduction in width of the gate, resulting in increased the leakage current. With the channel size continuing to shrink, the improvements can no longer resolve the increasingly significant short-channel effect.
In order to solve the problem of short-channel effect, a three-dimensional Fin Field-Effect Transistor (FinFET) has been proposed. A FinFET is a transistor with a fin-shaped channel structure, in which some surfaces of a thin fin act as the channel, allowing enhanced operating current, and thus avoiding the short-channel effect in a conventional transistor.
As shown in FIG. 1, a structural diagram of an existing FinFET, comprising: a fin 100; a gate 102 on the upper surface and the sides of the fin; and source and drain regions 104 at respective ends of the fin. Generally, forming of the FinFET comprises: forming a fin 100 and a gate 10; forming source and drain regions 104 at respective ends of the fin; and forming a contact plug on the gate 102, the source region 104 and the drain region 106.
However, the method above for forming a FinFET device has the problem that, in formation of the contact plug, the contact plug should be aligned with the gate, the source region and the drain region, and as the level of integration increases, the distance between gates is shortening, resulting in difficulty in the alignment of the contact plug and poor alignment accuracy. For example, the contact plug portion at the source/drain region may come into contact with the gate, or, the contact plug portion at the gate may come into contact with the source/drain region, directly leading to a short circuit of the device. Or, even if isolation between the contact plug at the source/drain region and the gate is realized, a large parasitic overlap capacitance will be formed therebetween, this may still reduce the AC performance and the speed of the device.